1. Field of the Invention
The present invention relates generally to integrated circuit technology and, more specifically, the present invention relates to integrated circuit buffers.
2. Description of the Related Art
To achieve high performances in modern integrated circuits, it is often necessary to utilize high speed buffer circuits, such as for example input/output buffers. One common use for input/output buffers is to interface integrated circuits with buses. Input/output buffers that are coupled to buses are often required to drive external loads that are large in comparison with the internal loads other integrated circuits drive.
As integrated circuit technologies continue to advance, the frequencies at which the integrated circuits operate increase accordingly. It has been a considerable challenge for circuit designers to design buses that are able to match the speed performance of the core speed of modern CPUs. One reason for the difficulty of continuously increasing bus speeds to match the continuously increasing CPU core speeds is that input/output buffers connected to the buses must often operate across a wide variety of operating conditions. For instance, the performance of a buffer changes significantly over process, voltage and temperature variations. As these conditions change, the noise and response characteristics of the input/output buffers connected to the buses are effected. For stable operation, integrated circuit designers must often limit the speed at which the buffer circuits such as input/output buffers operate to accommodate the potential variations in conditions.
The utilization of impedance compensated input/output buffers is one prior art solution that integrated circuit designers have used to accommodate variations in conditions. Impedance compensated input/output buffers provide a mechanism to maintain the optimum characteristics of an input/output buffer over a wide range of operating conditions. Impedance compensation enables the output impedance of the input/output buffer to be varied in order to match the line impedance of a line connected to the input/output buffer. As a result, the output impedance of the integrated circuit buffers can be adjusted accordingly to reduce noise and thereby increase performance as process, voltage and temperature conditions change.
The slew rate of a buffer circuit is another characteristic that is effected by variations in conditions such as process, voltage and temperature. As externally terminated buses become more commonly implemented in integrated circuit systems, the slew rate characteristic of a buffer becomes an increasingly significant factor in high speed applications. Indeed, variations in process, voltage and temperature may cause corresponding variations in the slew rate as well as variations in the impedance of buffers.
It is appreciated that the significance of the impedance and slew rate of buffer circuits is relevant to a variety of integrated circuit applications and is therefore not limited only to input/output buffers. For example, power supply ringing or the simultaneous switching noise observed in power supplies in integrated circuits may also be attributed to slew rate variations of a buffer circuit as a consequence of changes in conditions.
What is desired is a method and an apparatus for adjusting both the slew rate and the impedance of buffer circuits in order to compensate for variations in conditions such as process, voltage and temperature in integrated circuits. Such a method and apparatus should be readily implemented in integrated circuits with minimal area to maximize the performance of buffer circuits over a variety operating conditions.